元の名称記録: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE; STMicroelectronics (Crolles 2) SAS; STMicroelectronics S.r.l.; STMicroelectronics (Rousset) SAS; UNIVERSITE D'AIX MARSEILLE

The present disclosure relates to a memory cell () and to a method of erasing the memory cell (). The memory cell comprises a doped well () of a first conductivity type and a transistor (T). Transistor (T) comprises a doped first region () of a second conductivity type opposite to the first conductivity type, the first doped region extending in the doped well (); a buried doped channel () of the second conductivity type extending in the doped well (); and a gate stack () resting on the doped well (), above the buried doped channel (). The gate stack () comprises a first layer () adapted to trap charges, a second insulating layer () resting on the first layer and a third conductive layer () resting on the second layer.