元の名称記録: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

A method of training model for manufacturing a semiconductor device is provided. Training image data is collected from at least two wafer images on a same wafer. A metrology error function is determined according to the contour difference between at least two wafer images. A metrology-aware correction model including an optical proximity correction (OPC) model and a metrology model is trained based on the metrology error function associated with the metrology model, to obtain a trained OPC model and a trained metrology model.

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, at least one capacitor structure and a plurality of conductive vias. The semiconductor substrate has a plurality of substrate regions formed in a front side of the semiconductor substrate. The capacitor structure is formed over the front side of the semiconductor substrate and along sidewalls of the substrate regions. The capacitor structure includes a plurality of electrodes and a plurality of capacitor dielectric layers alternately disposed on the semiconductor substrate; and a plurality of connecting structures. Each connecting structure is electrically coupled to one of the plurality of electrodes. Tops of the connecting structures are coplanar with each other and substantially parallel to the front side of the semiconductor substrate. Each of the conductive vias is coupled to one of the electrodes.