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案件記録

Physical Quantity Detection Circuit And Physical Quantity Detection Device

発明審査中
1閲覧数
10請求項 · 1 独立
§ Ⅰ

案件概要

発明者

Kaoru ICHINOSE; Hideo HANEDA; Noriyuki MURASHIMA; Tomoaki TAKAHASHI

IPC分類

G1C 19/5776H3F 3/45

CPC分類

G1C19/5776H3F3/45475

A physical quantity detection circuit includes: a physical quantity detection signal output circuit that includes an amplifier circuit that amplifies a signal output from a physical quantity detection element, and outputs a physical quantity detection signal corresponding to a physical quantity; a failure diagnosis signal output circuit that outputs a failure diagnosis signal based on a signal output from at least one of a plurality of amplifiers included in the amplifier circuit; a failure diagnosis circuit that performs failure diagnosis based on the failure diagnosis signal and outputs a failure flag indicating a result of the failure diagnosis; a mask signal output circuit that compares a level of a signal output from each of the plurality of amplifiers with each of a plurality of set detection levels and outputs a mask signal based on a result of the comparison; and a disabling determination circuit that disables the failure flag based on the mask signal.

原文(中国語)

A physical quantity detection circuit includes: a physical quantity detection signal output circuit that includes an amplifier circuit that amplifies a signal output from a physical quantity detection element, and outputs a physical quantity detection signal corresponding to a physical quantity; a failure diagnosis signal output circuit that outputs a failure diagnosis signal based on a signal output from at least one of a plurality of amplifiers included in the amplifier circuit; a failure diagnosis circuit that performs failure diagnosis based on the failure diagnosis signal and outputs a failure flag indicating a result of the failure diagnosis; a mask signal output circuit that compares a level of a signal output from each of the plurality of amplifiers with each of a plurality of set detection levels and outputs a mask signal based on a result of the comparison; and a disabling determination circuit that disables the failure flag based on the mask signal.

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