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案件記録

COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) MULTI-WELL APPARATUS FOR ELECTRICAL CELL ASSESSMENT

発明審査中
3閲覧数
16請求項 · 2 独立
§ Ⅰ

案件概要

発明者

Donhee Ham; Wenxuan Wu; Jeffrey T. Abbott; Henry Julian Hinton; Hongkun Park

IPC分類

G1N 33/487B1L 3/

CPC分類

G1N33/48728B1L3/50853B1L2300/636B1L2300/645B1L2300/829

Disclosed herein are semiconductor devices to provide a CMOS-compatible, wafer-scale, multi-well platform that can be used for biomedical or other applications, and methods to operate the same. In some embodiments, circuitry is provided underneath a multiple-well array to electrically interface with electrodes in the wells. To interface with electrodes in a large array, circuitry may be fabricated on a single silicon (Si) wafer having a dimension that is at least the same or larger than that of the multiple-well array. According to one aspect of the present disclosure, standard CMOS fabrication process such as those known to be used in a standard semiconductor foundry may be used without expensive customization for complex fabrication procedures. This may help the production cost to be lowered in some cases.

原文(中国語)

Disclosed herein are semiconductor devices to provide a CMOS-compatible, wafer-scale, multi-well platform that can be used for biomedical or other applications, and methods to operate the same. In some embodiments, circuitry is provided underneath a multiple-well array to electrically interface with electrodes in the wells. To interface with electrodes in a large array, circuitry may be fabricated on a single silicon (Si) wafer having a dimension that is at least the same or larger than that of the multiple-well array. According to one aspect of the present disclosure, standard CMOS fabrication process such as those known to be used in a standard semiconductor foundry may be used without expensive customization for complex fabrication procedures. This may help the production cost to be lowered in some cases.

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