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案件記録

MEMORY DEVICE AND MEMORY SYSTEM FOR PERFORMING PARTIAL WRITE OPERATION, AND OPERATING METHOD THEREOF

発明審査中
2閲覧数
16請求項 · 3 独立
§ Ⅰ

案件概要

IPC分類

G6F 3/6

CPC分類

G6F3/614G6F3/652G6F3/659G6F3/673

A memory system includes a controller configured to transmit a reset write command and reset write data, and transmit a set write command and set write data; and at least one memory device configured to generate seed data by performing a first operation on the reset write data and read data read out from a target memory area in response to the reset write command, generate write data by performing a second operation on the seed data and the set write data in response to the set write command, and write back the write data to the target memory area.

原文(中国語)

A memory system includes a controller configured to transmit a reset write command and reset write data, and transmit a set write command and set write data; and at least one memory device configured to generate seed data by performing a first operation on the reset write data and read data read out from a target memory area in response to the reset write command, generate write data by performing a second operation on the seed data and the set write data in response to the set write command, and write back the write data to the target memory area.

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