CONFIGURABLE WRITE PROCESSING SPEEDS AT A MEMORY SYSTEM

原文（中国語）

Methods, systems, and devices for configurable write processing speeds at a memory system are described. The described techniques provide for a memory system to slow a write processing speed when the memory system identifies that entries within an active foreground changelog (AL) correspond to a threshold quantity of memory regions. Slowing the write processing speed may allow for additional time for the memory system flush logical-to-physical (L2P) mappings from a background changelog (BL) while still receiving write commands and populating the AL with new L2P mappings. For example, slowing the write processing speed may increase a duration associated with new L2P mappings within the AL satisfying the threshold quantity of memory regions and may enable the memory system to increase the threshold quantity of memory regions without incurring additional latency when flushing L2P mappings to the memory arrays.