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案件記録

MEMORY DEVICE AND OPERATING METHOD THEREOF

発明審査中
2閲覧数
20請求項 · 3 独立
§ Ⅰ

案件概要

発明者

Yi-Lun LU; Tai-Hao WEN; Yu-Chen CHANG; Win-San KHWA; Jui-Jen WU; Meng-Fan CHANG

IPC分類

G6F 7/523G6F 7/50

CPC分類

G6F7/523G6F7/50

A memory device includes a memory array configured to store weight data; a control logic configured to transmit input data to activate different numbers of multiple word lines in each of multiple cycles of multiply-and-accumulate (MAC) operations on the weight data and the input data; and multiple read circuits coupled to the memory array through multiple bit lines, and configured to generate, in response to a control signal, multiple read voltages based on multiple reference voltages in the cycles of MAC operations to the bit lines. The reference voltages are different from each other.

原文(中国語)

A memory device includes a memory array configured to store weight data; a control logic configured to transmit input data to activate different numbers of multiple word lines in each of multiple cycles of multiply-and-accumulate (MAC) operations on the weight data and the input data; and multiple read circuits coupled to the memory array through multiple bit lines, and configured to generate, in response to a control signal, multiple read voltages based on multiple reference voltages in the cycles of MAC operations to the bit lines. The reference voltages are different from each other.

外部リソース