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案件記録

GPU DIE ID VIRTUALIZATION IN CHIPLET

発明審査中
20請求項 · 3 独立
§ Ⅰ

案件概要

発明者

HaiKun Dong; Alexander Fuad Ashkar; Anthony Asaro; Fang Xia; XiaoJing Ma; Yong Zhang; ZengRong Huang; Qian Zong; ShenYuan Chen; WenBin Zhang

IPC分類

G6F 9/455G6F 9/48

CPC分類

G6F9/45558G6F9/45545G6F9/4881G6F2009/45583

An apparatus and method for efficiently accessing hardware resources in a virtualized environment. In various implementations, a computing system includes a first processing circuit and a second processing circuit that is a parallel data processing circuit. The second processing circuit includes multiple subdivisions, each with compute circuits, a memory subsystem, and a command processing circuit. The hypervisor running on the first processing circuit divides the second processing circuit into multiple partitions, each with a guest operating system and one or more subdivisions. A single mapping of multiple mappings includes a virtual function identifier that specifies a guest operating system, a virtual hardware resource identifier, and a corresponding physical hardware resource identifier. The hypervisor sends the mappings to at least the second processing circuit that uses the mappings to perform translations during execution of tasks. The first processing circuit does not perform translations.

原文(中国語)

An apparatus and method for efficiently accessing hardware resources in a virtualized environment. In various implementations, a computing system includes a first processing circuit and a second processing circuit that is a parallel data processing circuit. The second processing circuit includes multiple subdivisions, each with compute circuits, a memory subsystem, and a command processing circuit. The hypervisor running on the first processing circuit divides the second processing circuit into multiple partitions, each with a guest operating system and one or more subdivisions. A single mapping of multiple mappings includes a virtual function identifier that specifies a guest operating system, a virtual hardware resource identifier, and a corresponding physical hardware resource identifier. The hypervisor sends the mappings to at least the second processing circuit that uses the mappings to perform translations during execution of tasks. The first processing circuit does not perform translations.

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