INTERRUPT INTEGRITY CHECK
案件概要
出願人
STMicroelectronics International N.V.
発明者
Roberto Colombo; Vivek Mohan Sharma
IPC分類
CPC分類
According to an embodiment, an interrupt checker circuit includes a timestamp checker circuit having a first input terminal coupled to an interrupt signal. A second input terminal of the timestamp checker circuit is configured to receive a global time reference. The timestamp checker circuit is configured to record a first timestamp corresponding to a first interrupt event at the first input terminal of the timestamp checker circuit based on the global time reference, record a second timestamp corresponding to a second interrupt event at the first input terminal of the timestamp checker circuit based on the global time reference, and compare a time difference between the second timestamp and the first timestamp to an expected duration and, based thereon, generate an error signal in response to the time difference being outside the expected duration.
原文(中国語)
According to an embodiment, an interrupt checker circuit includes a timestamp checker circuit having a first input terminal coupled to an interrupt signal. A second input terminal of the timestamp checker circuit is configured to receive a global time reference. The timestamp checker circuit is configured to record a first timestamp corresponding to a first interrupt event at the first input terminal of the timestamp checker circuit based on the global time reference, record a second timestamp corresponding to a second interrupt event at the first input terminal of the timestamp checker circuit based on the global time reference, and compare a time difference between the second timestamp and the first timestamp to an expected duration and, based thereon, generate an error signal in response to the time difference being outside the expected duration.
外部リソース