Asymmetrical Last Level Cache
案件概要
発明者
Mahesh Subramony
IPC分類
CPC分類
An asymmetrical last level cache is described. In one or more implementations, a system includes a first set of cores with an associated first last level cache and a second set of cores with an associated second last level cache. The first and second last level caches are asymmetrical, meaning they have differing characteristics such as size, speed, replacement policy, or associativity. This configuration allows for dynamic allocation of tasks to the cores based on a combination of the performance characteristics of the cores and the attributes of their associated last level caches.
原文（中国語）
An asymmetrical last level cache is described. In one or more implementations, a system includes a first set of cores with an associated first last level cache and a second set of cores with an associated second last level cache. The first and second last level caches are asymmetrical, meaning they have differing characteristics such as size, speed, replacement policy, or associativity. This configuration allows for dynamic allocation of tasks to the cores based on a combination of the performance characteristics of the cores and the attributes of their associated last level caches.
外部リソース