検索に戻る
案件記録

INTEGRATED CIRCUIT FLOORPLAN GENERATION USING GENERATIVE ARTIFICIAL INTELLIGENCE MODELS

発明審査中
2閲覧数
20請求項 · 3 独立
§ Ⅰ

案件概要

発明者

Payal AGARWAL; Rishubh KHURANA; Andriy TEMKO; Mysore SRIRAM

IPC分類

G6F 30/392G6F 30/27

CPC分類

G6F30/392G6F30/27

Certain aspects of the present disclosure provide techniques and apparatus for generating a layout of an integrated circuit using machine learning techniques. An example method generally includes generating a random floorplan including a random arrangement of a plurality of circuit blocks representing components of the integrated circuit. A floorplan representing a candidate layout for the integrated circuit is generated using a generative artificial intelligence model and the random floorplan. Generally, the generative artificial intelligence model may be trained to generate the floorplan based on features associated with the plurality of circuit blocks including one or more geometric conditioning features. The generated floorplan is output for fabricating one or more samples of the integrated circuit.

原文(中国語)

Certain aspects of the present disclosure provide techniques and apparatus for generating a layout of an integrated circuit using machine learning techniques. An example method generally includes generating a random floorplan including a random arrangement of a plurality of circuit blocks representing components of the integrated circuit. A floorplan representing a candidate layout for the integrated circuit is generated using a generative artificial intelligence model and the random floorplan. Generally, the generative artificial intelligence model may be trained to generate the floorplan based on features associated with the plurality of circuit blocks including one or more geometric conditioning features. The generated floorplan is output for fabricating one or more samples of the integrated circuit.

外部リソース