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案件記録

DEADLOCK-FREE MODIFICATION TO NETWORK-ON-CHIP TOPOLOGY

発明審査中
1閲覧数
20請求項 · 3 独立
§ Ⅰ

案件概要

IPC分類

G6F 30/394G6F 30/31G6F 115/2

CPC分類

G6F30/394G6F30/31G6F2115/2

Designing a network-on-chip (NoC) includes accessing an existing NoC topology having existing NoC elements, blockages and existing wire connections. The existing NoC elements include network interface units and switches. The designing further includes creating an updated NoC topology from the existing NoC topology, including adding at least one new wire connection to the existing wire connections. The designing further includes identifying turns and segments in the existing and new wire connections in the updated NoC topology; and ensuring that no cycles are created by the segments that form turns. The updated NoC topology is deadlock-free.

原文(中国語)

Designing a network-on-chip (NoC) includes accessing an existing NoC topology having existing NoC elements, blockages and existing wire connections. The existing NoC elements include network interface units and switches. The designing further includes creating an updated NoC topology from the existing NoC topology, including adding at least one new wire connection to the existing wire connections. The designing further includes identifying turns and segments in the existing and new wire connections in the updated NoC topology; and ensuring that no cycles are created by the segments that form turns. The updated NoC topology is deadlock-free.

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