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案件記録

DISPLAY DEVICE INCLUDING AN ASYMMETRICAL PATTERN

発明審査中
2閲覧数
20請求項 · 4 独立
§ Ⅰ

案件概要

発明者

Na Hyeon CHA; Jun Hyun PARK; Sun Kwun SON; Cheol-Gon LEE

IPC分類

G9G 3/32G9G 3/3233G9G 3/3266

CPC分類

G9G3/32G9G3/3233G9G3/3266G9G2300/43G9G2300/819G9G2310/267G9G2320/233

A display device includes: a substrate; a first scan line and a second scan line disposed on the substrate; a data line intersecting the first scan line and the second scan line; a first pixel circuit portion and a second pixel circuit portion adjacent to each other in a first direction with the data line therebetween; and a shielding pattern disposed between the first pixel circuit portion and the second pixel circuit portion, wherein each of the first pixel circuit portion and the second pixel circuit portion includes a first transistor including a first gate electrode connected to a first node, and a first electrode connected to a second node; and a second transistor connected between the first node and the data line and including a second gate electrode capable of receiving a first scan signal, and the shielding pattern includes an asymmetrical portion protruding toward the first pixel circuit portion in a plan view.

原文(中国語)

A display device includes: a substrate; a first scan line and a second scan line disposed on the substrate; a data line intersecting the first scan line and the second scan line; a first pixel circuit portion and a second pixel circuit portion adjacent to each other in a first direction with the data line therebetween; and a shielding pattern disposed between the first pixel circuit portion and the second pixel circuit portion, wherein each of the first pixel circuit portion and the second pixel circuit portion includes a first transistor including a first gate electrode connected to a first node, and a first electrode connected to a second node; and a second transistor connected between the first node and the data line and including a second gate electrode capable of receiving a first scan signal, and the shielding pattern includes an asymmetrical portion protruding toward the first pixel circuit portion in a plan view.

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