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案件記録

MEMORY DEVICE

発明審査中
2閲覧数
19請求項 · 3 独立
§ Ⅰ

案件概要

発明者

Tsuneo UENAKA; Tomoya INDEN; Shigehiro YAMAKITA

IPC分類

G11C 7/10G11C 7/6G11C 7/18

CPC分類

G11C7/1039G11C7/6G11C7/18

According to one embodiment, a memory device includes a first silicon substrate, a second silicon substrate, and a memory cell array. A first CMOS circuit is formed on the first silicon substrate. The second silicon substrate is provided above the first silicon substrate in a stacking direction. A second CMOS circuit is formed on the second silicon substrate. The memory cell array is provided above the second silicon substrate in the stacking direction. The memory cell array is connected to the first CMOS circuit and the second CMOS circuit and includes a plurality of memory cells arranged in the stacking direction of the first silicon substrate and the second silicon substrate.

原文(中国語)

According to one embodiment, a memory device includes a first silicon substrate, a second silicon substrate, and a memory cell array. A first CMOS circuit is formed on the first silicon substrate. The second silicon substrate is provided above the first silicon substrate in a stacking direction. A second CMOS circuit is formed on the second silicon substrate. The memory cell array is provided above the second silicon substrate in the stacking direction. The memory cell array is connected to the first CMOS circuit and the second CMOS circuit and includes a plurality of memory cells arranged in the stacking direction of the first silicon substrate and the second silicon substrate.

外部リソース