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案件記録

FACET TRAPPING FOR EPITAXIAL GROWTH

発明審査中
2閲覧数
21請求項 · 3 独立
§ Ⅰ

案件概要

発明者

Samuel Langer; Kenneth James Bogedahl; Ian C. Laboriante; Matthew Willford; Stephen McNary; Gregg Rawlings; Gordon Nielsen

IPC分類

H1L 21/2H1L 21/311H1L 29/6H1L 29/732

CPC分類

H1L21/2639H1L21/2694H1L21/31111H10D10/441H10D62/124

The present disclosure generally relates to semiconductor processing including facet trapping for an epitaxial growth process. In an example, a semiconductor device includes a first semiconductor material, a dielectric layer, and a second semiconductor material. The first semiconductor material includes a monocrystalline surface. The dielectric layer is over the first semiconductor material. The dielectric layer has an opening to the monocrystalline surface. The opening is defined at least in part by a sidewall of the dielectric layer and a cavity in the dielectric layer. The cavity is at the monocrystalline surface and under the sidewall. The second semiconductor material is over the first semiconductor material and on the monocrystalline surface. The second semiconductor material is at least partially in the opening through the dielectric layer. The cavity in the dielectric layer is configured to trap a facet of the second semiconductor material in the cavity.

原文(中国語)

The present disclosure generally relates to semiconductor processing including facet trapping for an epitaxial growth process. In an example, a semiconductor device includes a first semiconductor material, a dielectric layer, and a second semiconductor material. The first semiconductor material includes a monocrystalline surface. The dielectric layer is over the first semiconductor material. The dielectric layer has an opening to the monocrystalline surface. The opening is defined at least in part by a sidewall of the dielectric layer and a cavity in the dielectric layer. The cavity is at the monocrystalline surface and under the sidewall. The second semiconductor material is over the first semiconductor material and on the monocrystalline surface. The second semiconductor material is at least partially in the opening through the dielectric layer. The cavity in the dielectric layer is configured to trap a facet of the second semiconductor material in the cavity.

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