MODIFIED ETCH STOP LAYERS FOR FORMING GATE VIAS
案件概要
出願人
Taiwan Semiconductor Manufacturing Company, Ltd.
発明者
Guang-Hong Zheng; Yuan-Tien Tu; Chih-Yuan Ting; Chao-Cheng Chen; Yi-Chen Wang; Fang-Yu Lin; Sheng-Liang Pan; Guan-Xuan Chen; Chia Lin Yeh
IPC分類
CPC分類
One aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a source/drain (S/D) contact over an S/D feature; a gate structure over a channel region, where the channel region is adjacent the S/D feature; a first interlayer dielectric (ILD) layer over the gate structure and surrounding the S/D contact; an etch stop layer over the first ILD layer and the S/D contact, where the etch stop layer includes a first portion and a second portion, and the second portion is different from the first portion in chemical composition; a second ILD layer over the etch stop layer; and a gate via over the gate structure, where the gate via is surrounded by the second portion of the etch stop layer.
原文(中国語)
One aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a source/drain (S/D) contact over an S/D feature; a gate structure over a channel region, where the channel region is adjacent the S/D feature; a first interlayer dielectric (ILD) layer over the gate structure and surrounding the S/D contact; an etch stop layer over the first ILD layer and the S/D contact, where the etch stop layer includes a first portion and a second portion, and the second portion is different from the first portion in chemical composition; a second ILD layer over the etch stop layer; and a gate via over the gate structure, where the gate via is surrounded by the second portion of the etch stop layer.
外部リソース