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案件記録

DEVICE, METHOD AND SYSTEM TO PROVIDE ELECTRICAL COUPLING ACROSS ACTIVE LAYERS OF AN INTEGRATED CIRCUIT DIE

発明審査中
1閲覧数
20請求項 · 3 独立
§ Ⅰ

案件概要

発明者

Abhishek Anil Sharma; Sagar Suthram; Pushkar Ranade; Wilfred Gomes; Tahir Ghani; Anand Murthy

IPC分類

H1L 23/522H1L 21/768H1L 23/528

CPC分類

H1L23/5226H1L21/76877H1L23/5283

Techniques and mechanisms for an integrated circuit (IC) die to provide electrical coupling across active layers. In an embodiment, an IC die comprises a first active layer, a second active layer, first metallization layers between the first and second active layers, and second metallization layers on the second active layer. A via structure extends through one or more of the second metallization layers, and further through the second active layer and the first metallization layers, to a side of the first active layer. The via structure is electrically coupled to a first interconnect structure of the second metallization layers and a second interconnect structure which is on an opposite side of the first active layer. In another embodiment, a distal end of the via structure adjoins multiple vias which each extend from the second interconnect structure and at least partially through the first active layer.

原文(中国語)

Techniques and mechanisms for an integrated circuit (IC) die to provide electrical coupling across active layers. In an embodiment, an IC die comprises a first active layer, a second active layer, first metallization layers between the first and second active layers, and second metallization layers on the second active layer. A via structure extends through one or more of the second metallization layers, and further through the second active layer and the first metallization layers, to a side of the first active layer. The via structure is electrically coupled to a first interconnect structure of the second metallization layers and a second interconnect structure which is on an opposite side of the first active layer. In another embodiment, a distal end of the via structure adjoins multiple vias which each extend from the second interconnect structure and at least partially through the first active layer.

外部リソース