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案件記録

RECESSED INTERCONNECTS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

発明審査中
2閲覧数
20請求項 · 3 独立
§ Ⅰ

案件概要

発明者

Moshe DOLEJSI; Travis W. LAJOIE; Abhishek Anil SHARMA; Gregory J. GEORGE; Vishak VENKATRAMAN; Ya OU

IPC分類

H1L 23/528H1L 23/522H1L 23/532

CPC分類

H1L23/528H1L23/5226H1L23/53295

Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a conductive line on a conductive structure. An insulating cap is on a top of the conductive line. An ILD layer is adjacent to the conductive line, and the conductive line has an uppermost surface below an uppermost surface of the ILD layer. A conductive via is in the ILD layer and on another conductive structure. The conductive via is laterally separated from the conductive line by the insulating cap, and the conductive via has an uppermost surface above the uppermost surface of the conductive line.

原文(中国語)

Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a conductive line on a conductive structure. An insulating cap is on a top of the conductive line. An ILD layer is adjacent to the conductive line, and the conductive line has an uppermost surface below an uppermost surface of the ILD layer. A conductive via is in the ILD layer and on another conductive structure. The conductive via is laterally separated from the conductive line by the insulating cap, and the conductive via has an uppermost surface above the uppermost surface of the conductive line.

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