Power Module with Multi-Layer Substrate and Second Insulation Layer to Increase Power Density
案件概要
出願人
Texas Instruments Incorporated
発明者
Kwnag-Soo Kim; Vivek Kishorechand Arora; Woochan Kim
IPC分類
CPC分類
An example semiconductor package comprises a multi-layer substrate having a bottom metal layer, a top metal layer, and a first insulation layer between bottom metal layer and the top metal layer. A plurality of first conductive traces are formed in the top metal layer. A second insulation layer is disposed over the exposed portions of the first insulation layer and over segments of the first conductive traces. A plurality of second conductive traces formed on top of the second insulation layer. One or more semiconductor dies are mounted on the one or more second segments of the conductive traces. One or more bond wires couple the semiconductor dies to one or more of the second conductive traces. A mold compound covers at least a portion of the semiconductor dies, the second insulation layer, the first conductive traces, and the second conductive traces.
原文(中国語)
An example semiconductor package comprises a multi-layer substrate having a bottom metal layer, a top metal layer, and a first insulation layer between bottom metal layer and the top metal layer. A plurality of first conductive traces are formed in the top metal layer. A second insulation layer is disposed over the exposed portions of the first insulation layer and over segments of the first conductive traces. A plurality of second conductive traces formed on top of the second insulation layer. One or more semiconductor dies are mounted on the one or more second segments of the conductive traces. One or more bond wires couple the semiconductor dies to one or more of the second conductive traces. A mold compound covers at least a portion of the semiconductor dies, the second insulation layer, the first conductive traces, and the second conductive traces.
外部リソース