LITHOGRAPHIC SEAM IMPLEMENTATION FOR ACTIVE INTERCONNECT ROUTING ACROSS MULTIPLE RETICLE FIELDS

原文（中国語）

Integrated circuit dies, interposers, systems, and methods are described related to implementing seams between fields exposed using different lithographic exposures. First and second metallization stack regions or fields each implement signal and/or power routing and are separated by a seam therebetween. The seam includes conductive features that span the seam and interconnect the metallization stack regions. A test feature surrounds the metallization stack regions and includes metallization portions that also span the seams. The test feature is within a seal ring and, through electrical testing, validates the conductive features that span the seam.