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案件記録

PACKAGE STRUCTURE AND PREPARATION METHOD THEREOF

発明審査中
12閲覧数
17請求項 · 2 独立
§ Ⅰ

案件概要

発明者

Haijie CHEN; Jielei XIE

IPC分類

H1L 25/18H1L 23/H1L 23/538H1L 25/H1L 25/65H10B 80/H10D 80/30

CPC分類

H1L25/18H1L23/5386H1L24/8H1L24/16H1L25/657H1L25/50H10B80/H10D80/30H1L2224/8146H1L2224/16146H1L2224/16225H1L2225/6513H1L2225/6517H1L2225/6541H1L2924/1431

A package structure and a related preparation method thereof are disclosed. The package structure includes: an interposer; and a logic chip structure and a signal channel structure that are located on a surface of the interposer, where the logic chip structure includes a logic chip on a surface of the interposer and a power supply channel structure on a surface of the logic chip. A power supply layer of the logic chip is close to the power supply channel structure, which is electrically connected to a corresponding conductive structure to achieve power supply. A signal layer of the logic chip is close to the interposer and connected to the corresponding conductive structure to realize signal transmission. In this way, the power supply does not interfere with signals, and a logic error is avoided; and an overall voltage and power consumption of a finished package is significantly reduced.

原文(中国語)

A package structure and a related preparation method thereof are disclosed. The package structure includes: an interposer; and a logic chip structure and a signal channel structure that are located on a surface of the interposer, where the logic chip structure includes a logic chip on a surface of the interposer and a power supply channel structure on a surface of the logic chip. A power supply layer of the logic chip is close to the power supply channel structure, which is electrically connected to a corresponding conductive structure to achieve power supply. A signal layer of the logic chip is close to the interposer and connected to the corresponding conductive structure to realize signal transmission. In this way, the power supply does not interfere with signals, and a logic error is avoided; and an overall voltage and power consumption of a finished package is significantly reduced.

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