CLOCKING SYSTEM FOR A SYSTEM ON CHIP USING PLL
案件概要
出願人
Microsoft Technology Licensing, LLC
発明者
Charles Walter BOECKER; Eric Douglas GROEN; Subramanian KRISHNAMOORTHY; Shaishav Achyut DESAI; Gurupada MANDAL; Ravi SHIVNARAINE; Jaskarn S. JOHAL
IPC分類
CPC分類
The described technology provides a device including a phase locked loop (PLL) circuit, the PLL circuit including a voltage controlled oscillator (VCO) and a phase detector, and a voltage supply and transconductance cell (Gm) configured to drain a current Iout from the VCO based on a sensed voltage (Vsup_sense) input into the Gm, wherein the Gm cell is configured to generate an open_loop signal based on the Iout drain from the VCO.
原文（中国語）
The described technology provides a device including a phase locked loop (PLL) circuit, the PLL circuit including a voltage controlled oscillator (VCO) and a phase detector, and a voltage supply and transconductance cell (Gm) configured to drain a current Iout from the VCO based on a sensed voltage (Vsup_sense) input into the Gm, wherein the Gm cell is configured to generate an open_loop signal based on the Iout drain from the VCO.
外部リソース