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案件記録

AVERAGING A DIGITAL PHASE LOCKED LOOP OUTPUT FREQUENCY TO CALCULATE A PRESET VALUE FOR USE IN THE EVENT OF A LINK LOSS

発明審査中
3閲覧数
20請求項 · 3 独立
§ Ⅰ

案件概要

発明者

Peter Stinson; Pinninti Arjun

IPC分類

H3L 7/197H3L 7/91

CPC分類

H3L7/1974H3L7/91

Systems and methods for averaging a digital phase locked loop output frequency to calculate a preset value for use in the event of a link loss are disclosed. The method may include reading a fractional portion of an output of a digital phase locked loop (DPLL), calculating an integer portion of the output of the DPLL, and accumulating a predetermined number of samples of the fractional portion and the integer portion of the output of the DPLL. The method may include computing an average value of an output frequency of the DPLL over the predetermined number of samples, extracting a fractional portion and an integer portion of the average value of the output frequency of the DPLL, and loading the fractional portion and the integer portion of the average value of the output frequency of the DPLL as preset values in a fractional-N phase locked loop.

原文(中国語)

Systems and methods for averaging a digital phase locked loop output frequency to calculate a preset value for use in the event of a link loss are disclosed. The method may include reading a fractional portion of an output of a digital phase locked loop (DPLL), calculating an integer portion of the output of the DPLL, and accumulating a predetermined number of samples of the fractional portion and the integer portion of the output of the DPLL. The method may include computing an average value of an output frequency of the DPLL over the predetermined number of samples, extracting a fractional portion and an integer portion of the average value of the output frequency of the DPLL, and loading the fractional portion and the integer portion of the average value of the output frequency of the DPLL as preset values in a fractional-N phase locked loop.

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