METHODS AND DEVICES FOR TIME DOMAIN ADC SAMPLING AND FILTERING
案件概要
発明者
Amy WHITCOMBE; Peter KURAHASHI; Hechen WANG; Richard DORRANCE; Brent R. CARLTON
IPC分類
CPC分類
An analog to digital converter (ADC) circuit including: a voltage-controlled delay circuit (VCDC) configured to: sample a received analog signal based on an input clock signal to generate analog signal samples; generate an output signal representative of the input clock signal shifted in the time domain with a delay based on the analog signal samples; and a time to digital converter (TDC) coupled to the voltage-controlled delay circuit and configured to generate a digital output signal based on the output signal.
原文（中国語）
An analog to digital converter (ADC) circuit including: a voltage-controlled delay circuit (VCDC) configured to: sample a received analog signal based on an input clock signal to generate analog signal samples; generate an output signal representative of the input clock signal shifted in the time domain with a delay based on the analog signal samples; and a time to digital converter (TDC) coupled to the voltage-controlled delay circuit and configured to generate a digital output signal based on the output signal.
外部リソース