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案件記録

PARALLEL MACROBLOCK SCAN LINE DECODING WITH ERROR HANDLING

発明審査中
1閲覧数
20請求項 · 3 独立
§ Ⅰ

案件概要

発明者

Hiu-Fai Ricky Chan; James Michael Holland; Tsung-Han Yang; Jason Paul Neilson; Nekhil Baid; Ce Wang; Samuel Wong

IPC分類

H4N 19/176H4N 19/124H4N 19/129H4N 19/13H4N 19/174H4N 19/436H4N 19/60H4N 19/65H4N 19/70

CPC分類

H4N19/176H4N19/124H4N19/129H4N19/13H4N19/174H4N19/436H4N19/60H4N19/65H4N19/70

Systems, apparatus, articles of manufacture, and methods to perform parallel macroblock scan line decoding with error handling are disclosed. An example apparatus disclosed herein includes a first decoder circuit to decode a first macroblock scan line of an encoded video frame, the first decoder circuit to fetch the first macroblock scan line from memory based on a load balancing algorithm. The disclosed example apparatus also includes a second decoder circuit to decode a second macroblock scan line of the encoded video frame, the second macroblock scan line different from the first macroblock scan line, the second decoder circuit to fetch the second macroblock scan line from the memory based on the load balancing algorithm. In the disclosed example apparatus, the first decoder circuit is to decode the first macroblock scan line and the second decoder circuit is to decode the second macroblock scan line in parallel.

原文(中国語)

Systems, apparatus, articles of manufacture, and methods to perform parallel macroblock scan line decoding with error handling are disclosed. An example apparatus disclosed herein includes a first decoder circuit to decode a first macroblock scan line of an encoded video frame, the first decoder circuit to fetch the first macroblock scan line from memory based on a load balancing algorithm. The disclosed example apparatus also includes a second decoder circuit to decode a second macroblock scan line of the encoded video frame, the second macroblock scan line different from the first macroblock scan line, the second decoder circuit to fetch the second macroblock scan line from the memory based on the load balancing algorithm. In the disclosed example apparatus, the first decoder circuit is to decode the first macroblock scan line and the second decoder circuit is to decode the second macroblock scan line in parallel.

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