SEMICONDUCTOR MEMORY DEVICE
案件概要
発明者
Jeongsu KIM; Jinwoo HAN
IPC分類
CPC分類
A semiconductor memory device includes a memory cell array structure, the memory cell array structure comprising a cell substrate layer, a cell array element layer on the cell substrate layer, the cell array element layer including a cell transistor and a cell capacitor, and a cell bonding layer on the cell array element layer, a peripheral circuit structure stacked on the memory cell array structure, and the peripheral circuit structure comprising a peripheral epi layer, the peripheral epi layer having an upper surface facing an upward or downward direction, a peripheral circuit element layer on the peripheral epi layer, the peripheral circuit element layer including a peripheral transistor, an etch stopping layer on a lower surface of the peripheral epi layer, and a peripheral bonding layer bonded to the cell bonding layer.
原文(中国語)
A semiconductor memory device includes a memory cell array structure, the memory cell array structure comprising a cell substrate layer, a cell array element layer on the cell substrate layer, the cell array element layer including a cell transistor and a cell capacitor, and a cell bonding layer on the cell array element layer, a peripheral circuit structure stacked on the memory cell array structure, and the peripheral circuit structure comprising a peripheral epi layer, the peripheral epi layer having an upper surface facing an upward or downward direction, a peripheral circuit element layer on the peripheral epi layer, the peripheral circuit element layer including a peripheral transistor, an etch stopping layer on a lower surface of the peripheral epi layer, and a peripheral bonding layer bonded to the cell bonding layer.
外部リソース