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案件記録

SEMICONDUCTOR MEMORY DEVICE

発明審査中
20請求項 · 3 独立
§ Ⅰ

案件概要

発明者

Jeongsu KIM; Jinwoo HAN

IPC分類

H10B 12/H1L 23/H1L 25/18H10D 80/30

CPC分類

H10B12/50H1L24/8H1L25/18H10B12/312H10D80/30H1L2224/8145H1L2924/1436

A semiconductor memory device includes a memory cell array structure, the memory cell array structure comprising a cell substrate layer, a cell array element layer on the cell substrate layer, the cell array element layer including a cell transistor and a cell capacitor, and a cell bonding layer on the cell array element layer, a peripheral circuit structure stacked on the memory cell array structure, and the peripheral circuit structure comprising a peripheral epi layer, the peripheral epi layer having an upper surface facing an upward or downward direction, a peripheral circuit element layer on the peripheral epi layer, the peripheral circuit element layer including a peripheral transistor, an etch stopping layer on a lower surface of the peripheral epi layer, and a peripheral bonding layer bonded to the cell bonding layer.

原文(中国語)

A semiconductor memory device includes a memory cell array structure, the memory cell array structure comprising a cell substrate layer, a cell array element layer on the cell substrate layer, the cell array element layer including a cell transistor and a cell capacitor, and a cell bonding layer on the cell array element layer, a peripheral circuit structure stacked on the memory cell array structure, and the peripheral circuit structure comprising a peripheral epi layer, the peripheral epi layer having an upper surface facing an upward or downward direction, a peripheral circuit element layer on the peripheral epi layer, the peripheral circuit element layer including a peripheral transistor, an etch stopping layer on a lower surface of the peripheral epi layer, and a peripheral bonding layer bonded to the cell bonding layer.

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