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案件記録

STORAGE DEVICE, STORAGE SYSTEM, AND OPERATION METHOD OF STORAGE DEVICE

発明審査中
21請求項 · 4 独立
§ Ⅰ

案件概要

発明者

Minho Kim; Kyungsoo Kim

IPC分類

H10B 41/41H1L 25/65H1L 25/10H1L 25/18H10B 10/H10B 12/H10B 41/35H10B 43/35H10B 43/40H10D 88/

CPC分類

H10B41/41H1L25/18H10B10/18H10B12/50H10B41/35H10B43/35H10B43/40H10D88/H1L25/657H1L25/105H1L2224/8145H1L2224/9181

A storage device includes a first semiconductor structure having a first cell area, with memory cells disposed on a first semiconductor substrate, and a first metal pad disposed above the first cell area. A second semiconductor structure has a peripheral circuit area on a second semiconductor substrate and on which peripheral circuits are disposed, a second cell area including a plurality of second memory cells, and a second metal pad bonded to the first metal pad. A third semiconductor structure includes a memory controller disposed on a third semiconductor substrate and connected to a third metal pad through a connection via penetrating through the third semiconductor substrate. A connection structure penetrates through the second semiconductor substrate and connects the memory controller to the second semiconductor structure. The memory controller controls the first and second cell areas based on a signal applied from a host through the third metal pad.

原文(中国語)

A storage device includes a first semiconductor structure having a first cell area, with memory cells disposed on a first semiconductor substrate, and a first metal pad disposed above the first cell area. A second semiconductor structure has a peripheral circuit area on a second semiconductor substrate and on which peripheral circuits are disposed, a second cell area including a plurality of second memory cells, and a second metal pad bonded to the first metal pad. A third semiconductor structure includes a memory controller disposed on a third semiconductor substrate and connected to a third metal pad through a connection via penetrating through the third semiconductor substrate. A connection structure penetrates through the second semiconductor substrate and connects the memory controller to the second semiconductor structure. The memory controller controls the first and second cell areas based on a signal applied from a host through the third metal pad.

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