NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

原文（中国語）

According to one embodiment, a non-volatile semiconductor memory device includes a plurality of first interconnect layers stacked apart from each other, a memory pillar passing through the plurality of first interconnect layers, a local bit line electrically coupled to the memory pillar, a bit line, a plurality of second interconnect layers stacked apart from each other, a first pillar passing through the plurality of second interconnect layers and electrically coupled to the local bit line, a second pillar passing through the plurality of second interconnect layers and electrically coupled to the bit line and the first pillar, a plurality of third interconnect layers stacked apart from each other, and a third pillar passing through the plurality of third interconnect layers and electrically coupled to the bit line. At least one of the plurality of third interconnect layers is electrically coupled to the local bit line.