INTEGRATED CIRCUIT STRUCTURES HAVING STRESS-INDUCING FIN TRIM ISOLATION REGIONS BOUND BY GATE CUTS
案件概要
発明者
Leonard P. GULER; Saurabh ACHARYA; Izabela SAMEK; Charles H. WALLACE; Philip CHUNG
IPC分類
CPC分類
Integrated circuit structures having stress-inducing fin trim isolation regions bound by gate cuts are described. In an example, an integrated circuit structure includes an integrated circuit structure including a vertical stack of horizontal nanowires or a fin over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. The dielectric structure induces a stress on the vertical stack of horizontal nanowires or the fin. A dielectric gate cut plug is in contact with the gate structure and the dielectric structure, and is continuous from the gate structure to the dielectric structure.
原文（中国語）
Integrated circuit structures having stress-inducing fin trim isolation regions bound by gate cuts are described. In an example, an integrated circuit structure includes an integrated circuit structure including a vertical stack of horizontal nanowires or a fin over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. The dielectric structure induces a stress on the vertical stack of horizontal nanowires or the fin. A dielectric gate cut plug is in contact with the gate structure and the dielectric structure, and is continuous from the gate structure to the dielectric structure.
外部リソース