INTEGRATED CIRCUIT STRUCTURES HAVING DIFFERENTIATED DIELECTRIC BOUNDARY WALLS
案件概要
発明者
Yang ZHANG; Guowei XU; Tao CHU; Robin CHAO; Ting-Hsiang HUNG; Chia-Ching LIN; Kan ZHANG; Chun Wing YEUNG; Lin HU; Chung-Hsun LIN; Anand S. MURTHY; Feng ZHANG
IPC分類
CPC分類
Integrated circuit structures having differentiated dielectric boundary walls, and methods of fabricating integrated circuit structures having differentiated dielectric boundary walls, are described. For example, an integrated circuit structure includes a sub-fin in a trench isolation structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric boundary wall is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a portion of the trench isolation structure. The dielectric boundary wall has a composition including a metal and oxygen. A dielectric gate plug is on the dielectric boundary wall.
原文(中国語)
Integrated circuit structures having differentiated dielectric boundary walls, and methods of fabricating integrated circuit structures having differentiated dielectric boundary walls, are described. For example, an integrated circuit structure includes a sub-fin in a trench isolation structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric boundary wall is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a portion of the trench isolation structure. The dielectric boundary wall has a composition including a metal and oxygen. A dielectric gate plug is on the dielectric boundary wall.
外部リソース