TECHNOLOGIES FOR EPITAXIAL PEROVSKITE FERROELECTRIC TRANSISTORS ON BUFFERED SILICON
案件概要
発明者
Arnab Sen Gupta; Pratyush P. Buragohain; Punyashloka Debashis; Raseong Kim; Matthew V. Metz; Suehyun Park; John J. Plombon; Rachel A. Steinhardt; Ian Alexander Young
IPC分類
CPC分類
Technologies for epitaxial perovskite ferroelectric transistors on buffered silicon are disclosed. In an illustrative embodiment, a barrier layer of titanium nitride is deposited on a silicon substrate using domain matching epitaxy, which allows the titanium nitride to grow with relatively low stress and a low number of defects, despite a 22% misfit between the lattice constant for titanium nitride and that lattice constant for silicon. The barrier layer prevents silicon monoxide (SiO) from forming when oxides are grown as later layers. In some embodiments, some or all of the titanium nitride barrier layer may be used as a gate electrode for the transistor.
原文（中国語）
Technologies for epitaxial perovskite ferroelectric transistors on buffered silicon are disclosed. In an illustrative embodiment, a barrier layer of titanium nitride is deposited on a silicon substrate using domain matching epitaxy, which allows the titanium nitride to grow with relatively low stress and a low number of defects, despite a 22% misfit between the lattice constant for titanium nitride and that lattice constant for silicon. The barrier layer prevents silicon monoxide (SiO) from forming when oxides are grown as later layers. In some embodiments, some or all of the titanium nitride barrier layer may be used as a gate electrode for the transistor.
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