METHODS AND APPARATUS TO UTILIZE DEEP TRENCH CAPACITORS WITHIN ISOLATED TRANSISTORS
案件概要
発明者
Kumar Anurag Shrivastava; Viresh Sharnappa Chinchansure
IPC分類
CPC分類
An example apparatus includes: a first resistor having a first terminal coupled to a supply voltage terminal and a second terminal; a transistor having a gate terminal coupled to a first input terminal, a source terminal coupled to a second input terminal, a body terminal coupled to the source terminal, and a drain terminal coupled to the second terminal of the first resistor; a substrate terminal coupled to ground; an isolation terminal that separates the transistor from the substrate terminal; a second resistor having a first terminal coupled to the isolation terminal and a second terminal coupled to the supply voltage terminal; and a third resistor having a first terminal coupled to the source terminal of the transistor and a second terminal coupled to ground.
原文(中国語)
An example apparatus includes: a first resistor having a first terminal coupled to a supply voltage terminal and a second terminal; a transistor having a gate terminal coupled to a first input terminal, a source terminal coupled to a second input terminal, a body terminal coupled to the source terminal, and a drain terminal coupled to the second terminal of the first resistor; a substrate terminal coupled to ground; an isolation terminal that separates the transistor from the substrate terminal; a second resistor having a first terminal coupled to the isolation terminal and a second terminal coupled to the supply voltage terminal; and a third resistor having a first terminal coupled to the source terminal of the transistor and a second terminal coupled to ground.
外部リソース