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案件記録

METHODS AND APPARATUS TO UTILIZE DEEP TRENCH CAPACITORS WITHIN ISOLATED TRANSISTORS

発明審査中
75閲覧数
20請求項 · 3 独立
§ Ⅰ

案件概要

発明者

Kumar Anurag Shrivastava; Viresh Sharnappa Chinchansure

IPC分類

H1L 27/6H1L 21/762H1L 27/2

CPC分類

H10D84/811H1L21/76224H10D89/10

An example apparatus includes: a first resistor having a first terminal coupled to a supply voltage terminal and a second terminal; a transistor having a gate terminal coupled to a first input terminal, a source terminal coupled to a second input terminal, a body terminal coupled to the source terminal, and a drain terminal coupled to the second terminal of the first resistor; a substrate terminal coupled to ground; an isolation terminal that separates the transistor from the substrate terminal; a second resistor having a first terminal coupled to the isolation terminal and a second terminal coupled to the supply voltage terminal; and a third resistor having a first terminal coupled to the source terminal of the transistor and a second terminal coupled to ground.

原文(中国語)

An example apparatus includes: a first resistor having a first terminal coupled to a supply voltage terminal and a second terminal; a transistor having a gate terminal coupled to a first input terminal, a source terminal coupled to a second input terminal, a body terminal coupled to the source terminal, and a drain terminal coupled to the second terminal of the first resistor; a substrate terminal coupled to ground; an isolation terminal that separates the transistor from the substrate terminal; a second resistor having a first terminal coupled to the isolation terminal and a second terminal coupled to the supply voltage terminal; and a third resistor having a first terminal coupled to the source terminal of the transistor and a second terminal coupled to ground.

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