検索に戻る
案件記録

EXTENDED GATE AND STANDARD GATE INTEGRATION SCHEME

発明審査中
20請求項 · 3 独立
§ Ⅰ

案件概要

発明者

Ruqiang Bao; Anthony I-Chih Chou; Tushar Gupta

IPC分類

H1L 27/88H1L 21/28H1L 29/6H1L 29/423H1L 29/51H1L 29/66H1L 29/775H1L 29/786

CPC分類

H10D84/83H1L21/28238H10D64/518H10D64/685H10D64/693H10D30/14H10D30/43H10D30/6735H10D30/6757H10D62/121

Embodiments of the invention include a semiconductor structure having a first transistor including first channel regions, a high-k dielectric layer on the first channel regions, and gate material on the high-k dielectric layer. A second transistor includes second channel regions, a nitride layer on the second channel regions, the high-k dielectric layer on the nitride layer, and the gate material on the high-k dielectric layer. The first and second channel regions include a corresponding number of semiconductor layers.

原文(中国語)

Embodiments of the invention include a semiconductor structure having a first transistor including first channel regions, a high-k dielectric layer on the first channel regions, and gate material on the high-k dielectric layer. A second transistor includes second channel regions, a nitride layer on the second channel regions, the high-k dielectric layer on the nitride layer, and the gate material on the high-k dielectric layer. The first and second channel regions include a corresponding number of semiconductor layers.

外部リソース