L-SHAPED STACKED FIELD EFFECT TRANSISTOR ISOLATED WITH TOP AND BOTTOM GATES
案件概要
出願人
International Business Machines Corporation
発明者
Chen Zhang; Shahrukh Khan; Ruilong Xie; Shay Reboh
IPC分類
CPC分類
A semiconductor has a gate line with a gate line opening flanked by a pair of source/drains. In the gate line opening are a bottom transistor and a top transistor. The bottom transistor includes a bottom set of nanosheets wrapped by a bottom workfunction material while the top transistor includes a top set of nanosheets wrapped by a top workfunction material. A dielectric structure separates the bottom transistor and the top transistor. The dielectric structure includes a middle dielectric portion (which can be L-shaped), a first plug laterally contacting a first side of the middle dielectric portion and a second plug laterally contacting a second side of the middle dielectric portion.
原文(中国語)
A semiconductor has a gate line with a gate line opening flanked by a pair of source/drains. In the gate line opening are a bottom transistor and a top transistor. The bottom transistor includes a bottom set of nanosheets wrapped by a bottom workfunction material while the top transistor includes a top set of nanosheets wrapped by a top workfunction material. A dielectric structure separates the bottom transistor and the top transistor. The dielectric structure includes a middle dielectric portion (which can be L-shaped), a first plug laterally contacting a first side of the middle dielectric portion and a second plug laterally contacting a second side of the middle dielectric portion.
外部リソース