Power module and manufacturing method thereof
データ提供元:EPO OPS
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案件概要
出願番号
CN20171063230
発明者
LI HUI; YANG SHENGSONG; LIAO WENQI; YANG QINYAO; LI YAN; ZHANG JIANLI; ZENG QIULIAN
出願日
Jan 24, 2017
公開日
Oct 8, 2019
パテントファミリーID
62963201
IPC分類
CPC分類
[0001] This invention provides a power module and its manufacturing method. The power module includes: an insulating dielectric substrate, comprising a first conductive layer and a first insulating layer disposed on the first conductive layer, wherein the first insulating layer has a first conductive path; a second insulating layer, wherein the second insulating layer has a second conductive path; a patterned second conductive layer; and at least one power semiconductor chip embedded between the first and second insulating layers. The power semiconductor chip is electrically connected to the first conductive layer through the first conductive path and electrically connected to the second conductive layer through the second conductive path. Packaging eliminates the need for molding, saving production costs. Furthermore, the power semiconductor chip achieves electrical connection to the upper conductive layer by creating through-holes in the insulating layer and filling them with conductive material, reducing the module's size and facilitating miniaturization.
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