Chip aging method and device
データ提供元:EPO OPS
本文を取得できませんでした。取得済みの書誌情報は引き続き確認できます。
案件概要
出願番号
CN202310261232
発明者
JIAO HUIFANG; WAN JUN; ZHU GUOLIANG; DONG WEI; ZHOU XUE
出願日
Mar 13, 2023
公開日
Sep 13, 2024
パテントファミリーID
92659900
IPC分類
CPC分類
The invention discloses a chip aging method and device, the aging device is connected with a driving circuit of a chip, and the driving circuit comprises a phase inverter and at least one selection transistor; the device is connected with an input end of a phase inverter and a grid electrode of a selection transistor, an output end of the phase inverter is connected with a drain electrode of the selection transistor, and a source electrode of the selection transistor and a second power supply end of the phase inverter are connected with low voltage; a high voltage is connected to a first power supply end of the phase inverter. The method comprises the following steps: outputting a first level for forming a direct-current electric field between input and output of the phase inverter to the phase inverter; or outputting a second level for controlling the conduction of the first power supply end and the output end to the phase inverter, and outputting a third level for forming a direct-current electric field between the source electrode and the drain electrode of the selection transistor to the grid electrode of the selection transistor, so that the driving circuit with the quality problem fails after accelerated aging; and row or multi-row failure of the chip caused by medium time-dependent breakdown or hot carrier degradation of the driving circuit after leaving a factory is avoided.
EPO 調査資料
項目を選択すると、この公開文献の公式資料を取得します。
上の項目を選択して資料を取得してください。
外部リソース