SMT core controller, compiler and method for executing compiled runtime code on SMT core controller
データ提供元:EPO OPS
本文を取得できませんでした。取得済みの書誌情報は引き続き確認できます。
案件概要
出願番号
CN20228092077
発明者
PETUSHKOV IGOR VYACHESLAVOVICH; WANG KEBING; LAMPRET DAMJAN
出願日
Mar 17, 2022
公開日
Sep 27, 2024
パテントファミリーID
81648624
IPC分類
CPC分類
The synchronous multi-thread core controller is configured to receive compiled runtime code including a plurality of threads and further execute at least two of the plurality of threads in parallel using the memory. Further, the SMT core controller determines whether there is any storage collision between the at least two threads executing in parallel. And the SMT core controller cancels the fiber thread with any storage conflict, re-executes the fiber thread with the storage conflict, and submits any storage operation of the fiber thread without the storage conflict to the SMT core memory. Executing at least two of the plurality of threads in parallel can improve superscalar pipeline utilization and parallelism of a single thread. In addition, the SMT core controller may increase the overall throughput of multi-threaded execution while improving efficiency and improving single-threaded execution.
EPO 調査資料
項目を選択すると、この公開文献の公式資料を取得します。
上の項目を選択して資料を取得してください。
外部リソース