Shift register, gate drive circuit and display device
データ提供元:EPO OPS
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案件概要
出願番号
CN202322905081U
発明者
QIU YUANYOU
出願日
Oct 27, 2023
公開日
Jul 30, 2024
パテントファミリーID
92070779
IPC分類
The utility model provides a shift register, a gate drive circuit and a display device, and belongs to the technical field of display. The shift register comprises an input sub-circuit which is configured to control the potentials of a first node and a second node in response to a first clock signal; the first control sub-circuit is configured to control the potential of the first node in response to the signal of the second node and a third clock signal; the third clock signal is opposite to the first clock signal in time sequence; the pull-down sub-circuit is configured to control the potential of a sixth node in response to a third clock signal and the signal of the first node; the second control sub-circuit is configured to control the potential of a fifth node in response to a signal of a sixth node, a signal of a second node and a second clock signal; the second clock signal and the third clock signal have the same time sequence; the output sub-circuit is configured to output a first output signal in response to a signal of a sixth node; or, in response to the signal of the fifth node, outputting a second output signal.
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