원래 이름 기록: Advanced Micro Devices, Inc.; XILINX, INC.

Dynamically pooled allocation of memory buffer on spatial compute architectures, including analyzing, at compile-time, access patterns (e.g., cyclo-static execution/firing rules) of consumer and/or producer processes that have shared access to local memory of one or more compute tiles, and identifying situations in which multiple buffers can be replaced with a pooled buffer having a memory footprint that is less than a sum of the memory footprints of the multiple buffers. A compiler may identify instances of mutual exclusiveness in the execution patterns of the processes, differences in execution times between compute kernels of the processes, and/or variations in execution times of the kernels. The compiler may generate controller code and/or configuration parameters to enforce memory allocation/mapping at application run-time.

Dynamic allocation of work and data on a spatial compute architecture in which a lead dispatch node dynamically assigns a task of an application to a selected compute tile, and routes a corresponding active message to a local data memory pool of the selected compute tile. The active message may include instructions, data, and/or configuration parameters to enable the selected compute tile to execute the task. If there is insufficient space in the local data memory pool, the lead dispatch node routes the active message to shared memory or to a local data memory pool of another compute tile, and subsequently routes the active message to the local data memory pool of the selected compute tile when space is available. Alternatively, the lead dispatch node may forward the task and the active message to another lead dispatch node.