FEEDBACK SIGNALLING
개요
발명자
Michael Andrew CAMPBELL; Mark UNDERWOOD
IPC 분류
CPC 분류
An apparatus includes memory control circuitry to control access to at least one array of memory storage cells and to schedule received memory access requests targeting locations in the at least one array of memory storage cells. The apparatus also includes utilisation status determining circuitry to determine a utilisation status associated with accessing the array of memory storage cells, in which the utilisation status is indicative of a utilisation of a group of memory storage cells in the at least one array of memory storage cells. The apparatus includes feedback signalling circuitry to signal to a source of the received memory access requests feedback indicative of the determined utilisation status.
원문 (중국어)
An apparatus includes memory control circuitry to control access to at least one array of memory storage cells and to schedule received memory access requests targeting locations in the at least one array of memory storage cells. The apparatus also includes utilisation status determining circuitry to determine a utilisation status associated with accessing the array of memory storage cells, in which the utilisation status is indicative of a utilisation of a group of memory storage cells in the at least one array of memory storage cells. The apparatus includes feedback signalling circuitry to signal to a source of the received memory access requests feedback indicative of the determined utilisation status.