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기록

INSTRUCTION FETCHING

발명심사 중
1조회수
20청구항 · 3 독립항
§ Ⅰ

개요

발명자

Leonardo Luiz ECCO; Guillaume BOLBENES; Thibaut Elie LANOIS; Benoît Henri Pierre-Marie Matthieu WALLON

IPC 분류

G6F 9/30G6F 9/32G6F 12/891

CPC 분류

G6F9/3802G6F9/30047G6F9/3804

There is provided an apparatus, a method, a chip containing product, a system and a medium. The apparatus is provided with an instruction fetch queue for storage of instruction fetch entries, and prefetching circuitry configured, for each instruction fetch entry and in response to a determination that a block of instructions indicated by that instruction fetch entry is not present in instruction storage circuitry, to issue a request to fetch the block and to cause the block to be allocated to the instruction storage circuitry. The apparatus is also provided with control circuitry configured to suppress issuing the request in response to a number of outstanding requests meeting or exceeding a variable throttling threshold. The control circuitry is configured to derive the variable throttling threshold from properties of previously fetched blocks, the properties determined before or during storage of the previously fetched blocks in the instruction storage circuitry.

원문 (중국어)

There is provided an apparatus, a method, a chip containing product, a system and a medium. The apparatus is provided with an instruction fetch queue for storage of instruction fetch entries, and prefetching circuitry configured, for each instruction fetch entry and in response to a determination that a block of instructions indicated by that instruction fetch entry is not present in instruction storage circuitry, to issue a request to fetch the block and to cause the block to be allocated to the instruction storage circuitry. The apparatus is also provided with control circuitry configured to suppress issuing the request in response to a number of outstanding requests meeting or exceeding a variable throttling threshold. The control circuitry is configured to derive the variable throttling threshold from properties of previously fetched blocks, the properties determined before or during storage of the previously fetched blocks in the instruction storage circuitry.