MULTICORE INTERFERER GENERATION
개요
발명자
Christopher J. Ambrose; Simon E. Roper
IPC 분류
CPC 분류
A system for multi-core interferer generation includes a processor and a memory including instructions which, when executed by the processor, cause the system at least to perform generating an interference test for one or more processor cores based upon one or more configuration files; introducing interference to the one or more processor cores to generate one or more interference test results; and filtering the one or more test results by evaluating performance data against one or more expected result hypotheses, each defining benchmark execution behavior and tolerance thresholds.
원문 (중국어)
A system for multi-core interferer generation includes a processor and a memory including instructions which, when executed by the processor, cause the system at least to perform generating an interference test for one or more processor cores based upon one or more configuration files; introducing interference to the one or more processor cores to generate one or more interference test results; and filtering the one or more test results by evaluating performance data against one or more expected result hypotheses, each defining benchmark execution behavior and tolerance thresholds.