STORAGE CONTROLLER AND OPERATION METHOD THEREOF
개요
발명자
Junyong UHM; Jeongmin JO; Jaesub KIM; Jung-Gyu KIM; Kyung-Ho SHIN; Jaeguk AHN
IPC 분류
CPC 분류
According to an embodiment of present disclosure, a storage controller configured to communicate with a host device may be provided. The storage controller may include a completion buffer that is configured to store one or more completions, and transmit the one or more completions to the host device; a first core that is configured to generate a first completion and a first trim load value both corresponding to a first trim command received from the host device; and a trim performance control circuit that is configured to delay transmission of the first completion to the completion buffer based on the first trim load value, with the trim performance control circuit being connected to both the completion buffer and the first core.
원문 (중국어)
According to an embodiment of present disclosure, a storage controller configured to communicate with a host device may be provided. The storage controller may include a completion buffer that is configured to store one or more completions, and transmit the one or more completions to the host device; a first core that is configured to generate a first completion and a first trim load value both corresponding to a first trim command received from the host device; and a trim performance control circuit that is configured to delay transmission of the first completion to the completion buffer based on the first trim load value, with the trim performance control circuit being connected to both the completion buffer and the first core.