AVAILABILITY OF HARDWARE ACCELERATORS FOR PERFORMING ACCELERATOR OPERATIONS

원문 (중국어)

An apparatus comprises processing circuitry to execute instructions, and accelerator control interface circuitry to exchange control signals with at least one hardware accelerator configurable, based on instructions executed by the processing circuitry, to perform a delegated task. The accelerator control interface circuitry comprises control storage corresponding to a given hardware accelerator, the control storage configured to indicate availability of the given hardware accelerator. In response to determining that the control storage indicates unavailability of the given hardware accelerator, the accelerator control interface circuitry is configured to provide a launch outcome indication indicating to the processing circuitry that the given hardware accelerator is unavailable to perform an accelerator operation.