DEADLOCK-FREE MODIFICATION TO NETWORK-ON-CHIP TOPOLOGY
개요
발명자
Amir CHARIF
IPC 분류
CPC 분류
Designing a network-on-chip (NoC) includes accessing an existing NoC topology having existing NoC elements, blockages and existing wire connections. The existing NoC elements include network interface units and switches. The designing further includes creating an updated NoC topology from the existing NoC topology, including adding at least one new wire connection to the existing wire connections. The designing further includes identifying turns and segments in the existing and new wire connections in the updated NoC topology; and ensuring that no cycles are created by the segments that form turns. The updated NoC topology is deadlock-free.
원문 (중국어)
Designing a network-on-chip (NoC) includes accessing an existing NoC topology having existing NoC elements, blockages and existing wire connections. The existing NoC elements include network interface units and switches. The designing further includes creating an updated NoC topology from the existing NoC topology, including adding at least one new wire connection to the existing wire connections. The designing further includes identifying turns and segments in the existing and new wire connections in the updated NoC topology; and ensuring that no cycles are created by the segments that form turns. The updated NoC topology is deadlock-free.