TECHNIQUES FOR PERFORMING ENTANGLING GATES ON LOGICAL QUBITS AND RELATED SYSTEMS AND METHODS
개요
발명자
Robert J. Schoelkopf, III; Takahiro Tsunoda; James Teoh; Benjamin Chapman; Stijn de Graaf; William Kalfus; Jacob Curtis; Neel Thakur
IPC 분류
CPC 분류
Techniques are described for performing two-qubit gates on logical qubits. The two-qubit gates may be performed in a manner that is fault tolerant and/or that produces an indication of whether or not an error occurred during the gate. The robustness of the described techniques against errors is provided at the hardware level by engineering a system in which an ancilla qubit acts as flag states for certain errors. As such, manipulating the state of the system to counteract an error may not be necessary; rather, when errors occur the result of a gate may be filtered out, or performed again. In other cases, the error state may simply be recorded as an indication of quality of the state of the system. The techniques for performing two-qubit gates described herein may also be compatible with different bosonic encodings of logical qubits, of which illustrative examples are described.
원문 (중국어)
Techniques are described for performing two-qubit gates on logical qubits. The two-qubit gates may be performed in a manner that is fault tolerant and/or that produces an indication of whether or not an error occurred during the gate. The robustness of the described techniques against errors is provided at the hardware level by engineering a system in which an ancilla qubit acts as flag states for certain errors. As such, manipulating the state of the system to counteract an error may not be necessary; rather, when errors occur the result of a gate may be filtered out, or performed again. In other cases, the error state may simply be recorded as an indication of quality of the state of the system. The techniques for performing two-qubit gates described herein may also be compatible with different bosonic encodings of logical qubits, of which illustrative examples are described.