REDUCTION IN CHIP AREA THROUGH DESIGN-TECHNOLOGY CO-OPTIMIZATION

원문 (중국어)

Multi-stage charge pumps use a modular structure in which each stage include a pair of legs, or current paths, between the stage input and the stage output. Each leg includes a stage boosting capacitor having a first plate connected to the current path and a second plate connected to receive one of a pair of non-overlapping clock signals. Each leg has an NMOS charge transfer switch connected between the stage input and the first plate of the stage boosting capacitor and a PMOS charge transfer switch connected between the first plate of the stage boosting capacitor and the stage output. To reduce charge pump area, the NMOS and PMOS charge transfer switches are formed to have a same resistance value when in an on state, where to achieve this the NMOS charge transfer switches are formed with wider control gates than the PMOS charge transfer switches.