Semiconductor structure and manufacturing method thereof
개요
발명자
Hung-Chan Lin; Yu-Ping Wang; Chien-Ting Lin
IPC 분류
CPC 분류
The invention provides a semiconductor structure, which comprises an inter-metal dielectric layer disposed on the substrate, a metal interconnection disposed in the inter-metal dielectric layer, wherein at least a portion of a top surface of the inter-metal dielectric layer is lower than a top surface of the metal interconnection, a MTJ (magnetic tunneling junction) stacked structure disposed on the metal interconnection, and a SOT (spin orbit torque) layer arranged on the MTJ stacked structure, wherein the SOT layer comprises a first part with a thick thickness and two second parts with a thin thickness.
원문 (중국어)
The invention provides a semiconductor structure, which comprises an inter-metal dielectric layer disposed on the substrate, a metal interconnection disposed in the inter-metal dielectric layer, wherein at least a portion of a top surface of the inter-metal dielectric layer is lower than a top surface of the metal interconnection, a MTJ (magnetic tunneling junction) stacked structure disposed on the metal interconnection, and a SOT (spin orbit torque) layer arranged on the MTJ stacked structure, wherein the SOT layer comprises a first part with a thick thickness and two second parts with a thin thickness.