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기록

END-OF-CYCLE SIGNAL GENERATION CIRCUIT AND METHOD

발명심사 중
1조회수
20청구항 · 3 독립항
§ Ⅰ

개요

발명자

Sanjeev Kumar JAIN

IPC 분류

G11C 11/419G11C 7/22G11C 11/418H3K 3/37H3K 19/20

CPC 분류

G11C11/419G11C7/222G11C11/418H3K3/37H3K19/20

A signal generation circuit includes a loopback path and a signal generator including an inverter including an output terminal coupled to a first end of the loopback path, a transistor coupled between a second end of the loopback path and a power distribution node, a buffer including an input terminal configured to receive a clock signal, a first logic gate including a first input terminal coupled to the buffer input terminal, a second input terminal coupled to an output terminal of the buffer, and an output terminal coupled to an input terminal of the inverter and a gate of the transistor, and a second logic gate including a first input terminal coupled to the buffer input terminal, a second input terminal coupled to the second end of the loopback path, and an output terminal configured to output an output signal.

원문 (중국어)

A signal generation circuit includes a loopback path and a signal generator including an inverter including an output terminal coupled to a first end of the loopback path, a transistor coupled between a second end of the loopback path and a power distribution node, a buffer including an input terminal configured to receive a clock signal, a first logic gate including a first input terminal coupled to the buffer input terminal, a second input terminal coupled to an output terminal of the buffer, and an output terminal coupled to an input terminal of the inverter and a gate of the transistor, and a second logic gate including a first input terminal coupled to the buffer input terminal, a second input terminal coupled to the second end of the loopback path, and an output terminal configured to output an output signal.