SUSPEND-RESUME-GO TECHNIQUES FOR MEMORY DEVICES

원문 (중국어)

The memory device includes an array of memory cells that are arranged in word lines and are programmed to contain data. Circuitry is configured to erase the memory cells of the memory block in an erase operation. During erase, the circuitry is configured to begin an erase operation to erase the memory cells and suspend the erase operation for a first suspension. After the first suspension is completed, the circuitry is configured to resume the erase operation. The circuitry is then configured to receive an instruction to suspend the erase operation for a second suspension and dynamically determine a minimum resume latency based on a vulnerability of the memory block to erase errors. Only after the minimum resume latency has passed following the step of resuming the erase operation after the first suspension is completed, the circuitry is configured to suspend the erase operation for the second suspension.